Slowness of design process for integrated circuits (IC) reduces time to market, and can be a competitive disadvantage if other companies find faster processes.
In the past, an IC design process describes the IC logic in Very high speed IC Hardware Description Language (VHDL) or some other type of hardware description language, feeds VHDL into a simulation environment, and loads a netlist which describes the interconnection topology of the design into a hardware accelerator. The hardware accelerator typically is a chassis full of software programmable Field Programmable Gate Arrays (FPGAs). Software evaluates the netlist and partitions it so that the FPGAs can be programmed to emulate the topology of the proposed design. The designer then interacts with the hardware accelerator to emulate and evaluate the operation of the proposed IC design.
Typically, the IC design process is oriented towards a batch mode or single-user interactive mode. Such a single user environment restricts access to the hardware accelerator to a single designer, which hampers the design process.
Accordingly, it is an object of the invention to provide an IC design system which allows the designer to interact with the simulation environment and make more effective use of the hardware accelerator.
Another object of the invention is to allow multiple designers to interact with the simulation environment in order to reduce the design cycle time.
Other objects and advantages will be apparent to those of ordinary skill in the art after referring to the following figures and specification.